Host-Port Interface Timing - Texas Instruments TMS320C6201 Manual

timing requirements for host-port interface cycles
Figure 33)
NO NO.
1 t
su(SEL-HSTBL)
2 t
h(HSTBL-SEL)
3 t
w(HSTBL)
4 t
w(HSTBH)
10 t
su(SEL-HASL)
11 t
h(HASL-SEL)
12 t
su(HDV-HSTBH)
13 t
h(HSTBH-HDV)
14 t
h(HRDYL-HSTBL)
18 t
su(HASL-HSTBL)
19 t
h(HSTBL-HASL)
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface
†‡
cycles (see Figure 30, Figure 31, Figure 32, and Figure 33)
NO NO.
5 t
d(HCS-HRDY)
6 t
d(HSTBL-HRDYH)
7 t
oh(HSTBL-HDLZ)
8 t
d(HDV-HRDYL)
9 t
oh(HSTBH-HDV)
15 t
d(HSTBH-HDHZ)
16 t
d(HSTBL-HDV)
17 t
d(HSTBH-HRDYH)
20 t
d(HASL-HRDYH)
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
||
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

HOST-PORT INTERFACE TIMING

§
Setup time, select signals valid before HSTROBE low
§
Hold time, select signals valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
§
Setup time, select signals valid before HAS low
§
Hold time, select signals valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE shoul not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly.
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
PARAMETER PARAMETER
¶
Delay time, HCS to HRDY
Delay time, HSTROBE low to HRDY high
Output hold time, HD low impedance after HSTROBE low for an HPI read
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid
Delay time, HSTROBE high to HRDY high
Delay time, HAS low to HRDY high
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
†‡
(see Figure 30, Figure 31, Figure 32, and
#
||
•
HOUSTON, TEXAS 77251--1443
TMS320C6201
- -200
UNIT UNIT
MIN MAX
4 ns
2 ns
2P ns
2P ns
4 ns
2 ns
3 ns
2 ns
1 ns
2 ns
2 ns
- -200
UNIT UNIT
MIN MAX
1 9 ns
3 12 ns
4 ns
P -- 3 P + 3 ns
2 12 ns
3 12 ns
2 12 ns
3 12 ns
3 12 ns
47