Generation Of Dsp Subsystem Master Clock And Dsp Mmu Clock; Idle Control - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Reset, Clocking, Idle Control, and Boot
Figure 104. Generation of DSP Subsystem Master Clock and DSP MMU Clock
CK_GEN2
ARM_CKCTL[DSPMMUDIV(11:10)]

12.3 Idle Control

218 DSP Subsystem
Frequency divider
ARM_CKCTL[DSPDIV(7:6)]
Frequency divider
The DSP subsystem master clock, DSP_CK, feeds all the modules included
in the DSP module (section 1.2 lists these modules). The DSPDIV bits in the
clock control register (ARM_CKCTL) specify the divider value used to
generate DSP_CK from the DSP domain clock. By default, the DSPDIV bits
select the divide-by-one mode. The EN_DSPCK bit in the same register
enables the DSP_CK (by default DSP_CK is enabled).
The DSP MMU clock, DSPMMU_CK, is generated from the DSP domain clock
similarly to DSP_CK. The DSPMMUDIV bits in the ARM_CKCTL register
specify the divider value used to generate the DSPMMU_CK from the DSP
domain clock. By default, the DSPMMUDIV bits select the divide-by-one
mode. DSPMMU_CK can be shut off by setting the GL_PDE bit of the
DSPMMU_IDLE_CTRL register (section 6.5.17).
The OMAP clock generation and system reset module manages operations
such as the reset sequences, the clock generation function, the power-saving
modes, idle controls, and setup for the OMAP5912. The MPU manages the
master clock configuration for the OMAP5912 device.
For more information on OMAP clock architecture and control, see the
following documents: OMAP5912 Multimedia Processor Clocks Reference
Guide (SPRU751), the OMAP5912 Multimedia Processor OMAP3.2
Subsystem Reference Guide (SPRU749), and the OMAP5910 Dual-Core
Processor Clock Generation and System Reset Management Reference
Guide (SPRU678).
The DSP subsystem can be idled at two levels: at the DSP subsystem level
and at the DSP module level. Idling at the subsystem level is quick and simple;
however, it requires that the DSP subsystem be reset, thereby eliminating any
currently executing application. To preserve the state of the DSP subsystem,
the subsystem must be idled at the DSP module level. The following sections
describe both approaches.
Software clock enable
ARM_CKCTL[EN_DSPCK(13)]
Software clock enable
DSPMMU_IDLE_CTRL
[GL_PDE(1)]
DSP_CK
DSP
DSPMMU_CK
DSP
MMU
SPRU890A