HBM Genesis GEN5i User Manual page 338

Channel to Channel Phase Match
Using different filter selections (Wideband/Bessel/Bessel IIR) or different filter bandwidths will lead to phase mismatches between channels.
Channel to Channel phase difference
Fiber cable length compensation
Fiber cable delay
On-board Memory
Per card
Organization
Memory diagnostics
Storage sample size
Digital Events/Timer/Counter
Digital event inputs
Digital event outputs
Timer/Counter
Triggering
Channel trigger/qualifier
Pre- and post-trigger length
Trigger rate
Manual trigger (Software)
External Trigger In
Minimum pulse width
Send to External Trigger Out
External Trigger Out
Cross channel triggering
System trigger bus
Analog channel trigger levels
338
Maximum ± 10 ns
Yes, automatically when optical communication is established
5 ns/m; Delay compensated by cable length compensation
2 GB (1 GS)
Automatic distribution amongst enabled channels
Automatic memory test when system is powered and not recording
16 bits, 2 bytes/sample
Not supported
Not supported
Not supported
1 per channel; fully independent either trigger or qualifier
0 to full memory
400 triggers per second
Supported
Selection per card User selectable On/Off
Active edge Rising/Falling mainframe selectable, identical for all cards
500 ns
± 1 µs + maximum 1 sample period (for decimal and binary time base)
Delay
User can select to forward External Trigger In to the External Trigger Out BNC
Selection per card User selectable On/Off
Active level High / Low / Hold High; selectable per mainframe, identical for all cards
Pulse width High / Low: 12.8 µs
Hold high: Active from first mainframe trigger to end of recording
Pulse width created by mainframe
516 µs ± 1 µs + maximum 1 sample period using decimal time base
Delay
504 µs ± 1 µs + maximum 1 sample period using binary time base
Channels on card Logical OR; Analog triggers of all channels
Logical AND; Qualifiers of all channels
Cards in mainframe User selectable through system trigger bus
Selections: Send/Receive/Transceive (Send & Receive)
Connections 3 System trigger busses connecting all cards within mainframe
1 Master/Slave bus connecting all cards within mainframe and connecting all mainframes
when using Master/Slave option
Operation Logical OR of all triggers of all cards
Logical AND of all qualifiers of all cards
Levels Maximum 2 level detectors
Resolution 16 bit (0.0015 %); for each level
Direction Rising/Falling; Single direction control for both levels based on selected mode
Hysteresis 0.1 to 100 % of Full Scale; defines the trigger sensitivity
GEN5i
I2679-4.0 en