ST STM32WL55JC Reference Manual page 1430

Debug support (DBG)
38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2
(C2ROM2_PIDR2)
Address offset: 0xFE8
Reset value: 0x0000 000B
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVISION[3:0]: component revision number
0x0: rev r0p0
Bit 3 JEDEC: JEDEC assigned value
1: Designer ID specified by JEDEC
Bits 2:0 JEP106ID[6:4]: JEP106 identity code bits [6:4]
0x3: Arm
38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3
(C2ROM2_PIDR3)
Address offset: 0xFEC
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications
1430/1454
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
®
JEDEC code
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0453 Rev 2
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
REVISION[3:0]
r r r r
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
REVAND[3:0]
r r r r
RM0453
19 18 17
Res. Res. Res. Res.
3 2 1
JEDEC JEP106ID[6:4]
r r r
19 18 17
Res. Res. Res. Res.
3 2 1
CMOD[3:0]
r r r
16
0
r
16
0
r