Table 281. Tpiu Register Map And Reset Values - ST STM32WL55JC Reference Manual

Debug support (DBG)
Table 281. TPIU register map and reset values (continued)
Offset Register name
TPIU_PIDR2
0xFE8
Reset value
TPIU_PIDR3
0xFEC
Reset value
TPIU_CIDR0
0xFF0
Reset value
TPIU_CIDR1
0xFF4
Reset value
TPIU_CIDR2
0xFF8
Reset value
TPIU_CIDR3
0xFFC
Reset value
Refer to
38.12 Microcontroller debug unit (DBGMCU)
DBGMCU is a component containing a number of registers that control the power and clock
behavior in debug mode. It allows the debugger (or the debug software) to perform the
following tasks:
•
Maintain the clock and power to the processor cores when in low-power modes (Sleep,
Stop or Standby).
•
Maintain the clock and power to the system debug and trace components when in
low-power modes.
• Stop the clock to certain peripherals (such as watchdogs, timers, RTC) when either
processor core is stopped in debug mode.
DBGMCU registers are not reset by a system reset, only by a power on reset. They are
accessible to the debugger via the CPU1 AHB access port at base address 0xE0042000.
Note: DBGMCU is not a standard CoreSight component, consequently it does not appear in the
CPU1 ROM table.
1412/1454
Section 38.8: CPU1 ROM table for the register boundary addresses.
RM0453 Rev 2
RM0453
REVISION JEP106ID
[3:0] [6:4]
0 1 0 0 1 0 1 1
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0 1
PREAMBLE
CLASS[3:0]
[11:8]
1 0 0 1 0 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0 1
PREAMBLE[27:20]
1 0 1 1 0 0 0 1