ST STM32WL55JC Reference Manual page 1421

RM0453
Address in ROM
Component name
table
0xF0000008
0xF000000C
0xF0000010
0xF000000C to
0xF0000FC8
0xF0000FCC to
ROM table registers
0xF0000FFC
ROM2 occupies a 4-Kbyte, 32-bit wide chunk of APB-D address space, from 0xE00FF000
to 0xE00FFFFC.
Address in ROM
table
0xE00FF000
0xE00FF004
0xE00FF008
0xE00FF00C
0xE00FF010 to
0xE00FFFC8
0xE00FFFCC to
0xE00FFFFC
The topology for the CoreSight components in the CPU2 subsystem is shown in
Table 283. ROM1 table
Component base
Not used
Not used
Top of table
Reserved
Table 284. ROM2 table
Component Component base
name address
SCS 0xE000E000
DWT 0xE0001000
BPU 0xE0002000
Top of table
Reserved
ROM table
registers
Component
address address offset
-
-
-
-
-
Component
address offset
0xFFF0F000
0xFFF02000
0xFFF03000
-
-
-
RM0453 Rev 2
Debug support (DBG)
Size
- -
- -
- -
- -
- -
Size
4 KB
4 KB
4 KB
- -
- -
- -
Entry
0x00002002
0x10000002
0x00000000
0x00000000
See Table 285
Entry
0xFFF0F003
0xFFF02003
0xFFF03003
0x00000000
0x00000000
See Table 286
Figure 392.
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