ST STM32WL55JC Reference Manual page 1446

Revision history
40 Revision history
Date Revision
5-Nov-2020 1
24-Jun-2021 2
1446/1454
Table 288. Document revision history
Initial version
Updated:
– Patented technology and errata sheet in the
– Section 4.3.2: Empty check
– OPTVAL in Section 4.4.2: Option bytes programming
– OPTNV description in
– Section 5.1: Sub-GHz radio introduction
– Section 5.2: Sub-GHz radio main features
– Section 5.5.5: Generic framing
– New functionality in Section 5.6: Sub-GHz radio data buffer
– Section 5.7.2: Sleep mode
– Note removed in Set_RfFrequency() command
– Section 5.9: Sub-GHz radio application configuration
– Danger note removed in
– Section 5.10.22: Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR)
– Figure 20: Brownout reset waveform
– PVD naming in Section 6.6.2: PWR control register 2 (PWR_CR2)
Power status register 2 (PWR_SR2)
– First sentence in Section 7.1.2: System reset
– External source (HSE32 TXCO)
– First sentence of Section 8.4: HSEM registers
– Caution in Section 14.4.6: DMAMUX request line multiplexer
– Note in Section 14.4.7: DMAMUX request generator
– New note in Polynomial programmability
– Figure 58: ADC block diagram
– Formula in Figure 22.5: RNG processing time
– Table 127: Interrupt control bits
– Table 134: CTR mode initialization vector definition
– Table 137: Initialization of AES_IVRx registers in CCM mode
– Section 24.3.4: PKA public key acceleration
– Table 149: Montgomery multiplication
– Section 24.5: Example of configurations and processing times
– Table 174: PKA interrupt requests
– AFIO renamed in Section 26: General-purpose timer (TIM2)
– New note in Section 28.4.7: Trigger multiplexer
– Some bit descriptions in
– Table 248: Error calculation for programmed baud rates at
lpuart_ker_ck_pres = 32.768 kHz
RM0453 Rev 2
Changes
Introduction
Section 4.10.5: FLASH status register (FLASH_SR)
Section 5.10: Sub-GHz radio registers
Section 28.7.2: LPTIM interrupt clear register (LPTIM_ICR)
RM0453
and Section 6.6.6: