ST STM32WL55JC Reference Manual page 1419

RM0453
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 stop in CPU2 debug
0: Normal operation. TIM17 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM17 is frozen while CPU2 is in debug mode.
Bit 17 DBG_TIM16_STOP: TIM16 stop in CPU2 debug
0: Normal operation. TIM16 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM16 is frozen while CPU2 is in debug mode.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 stop in CPU2 debug
0: Normal operation. TIM1 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM1 is frozen while CPU2 is in debug mode.
Bits 10:0 Reserved, must be kept at reset value.
38.12.9 DBGMCU register map and reset values
Offset Register name
DBGMCU_
IDCODER
0x000
Reset value
DBGMCU_CR
0x004
Reset value
0x008-
Reserved
0x038
DBGMCU_
APB1FZR1
0x03C
Reset value
DBGMCU_
C2APB1FZR1
0x040
Reset value
DBGMCU_
APB1FZR2
0x044
Reset value
Table 282. DBGMCU register map and reset values
REV_ID[15:0]
x x x x x x x x x
0 0
0 0
x x x x x x x
Reserved.
0 0
0 0
RM0453 Rev 2
Debug support (DBG)
DEV_ID[11:0]
0 1 0 0 1 0 0 1
0 0 0
0 0
0 0
0 1 1 1
0 0 0
0
0
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