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Debug support (DBG)
38.11.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
38.11.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.11.21 CPU 1 TPIU register map and reset values
Offset Register name
TPIU_SSPSR
0x000
Reset value
TPIU_CSPSR
0x004
Reset value
0x008 to
Reserved
0x00C
TPIU_ACPR
0x010
Reset value
1410/1454
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Table 281. TPIU register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
PORTSIZE[31:0]
0
0
0
0
0
0
0
0
0
PORTSIZE[31:0]
0
0
0
0
0
0
0
0
0
Reserved.
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[19:12]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[27:20]
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRESCALER[12:0]
0
0
0
0
0
0
0
RM0453
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
0
0
1
1
1 1
0
0
0
0
0 1
0
0
0
0
0 0
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