ST STM32WL55JC Reference Manual page 1440

Debug support (DBG)
Table 287. CPU2 BPU register map and reset values (continued)
Offset Register name
BPU_REMAPR
0x004
Reset value
BPU_COMP0-7R
0x008 to
0x024
Reset value
0x02C-
Reserved
0xFCC
BPU_PIDR4
0xFD0
Reset value
0xFD4-
Reserved
0xFDC
BPU_PIDR0
0xFE0
Reset value
BPU_PIDR1
0xFE4
Reset value
BPU_PIDR2
0xFE8
Reset value
BPU_PIDR3
0xFEC
Reset value
BPU_CIDR0
0xFF0
Reset value
BPU_CIDR1
0xFF4
Reset value
BPU_CIDR2
0xFF8
Reset value
BPU_CIDR3
0xFFC
Reset value
Refer to
1440/1454
0
0 0 0 0 0 0 0
Section 38.13: CPU2 ROM tables
COMP[26:0]
0 0 0 0 0 0 0 0 0
Reserved.
Reserved.
for the register boundary addresses.
RM0453 Rev 2
0 0 0 0 0 0 0 0 0
F4KCOUNT
[3:0]
0 0
0 0
JEP106ID
[3:0]
1 0
REVISION
[3:0]
0 0
REVAND[3:0] CMOD[3:0]
0 0
0 0
CLASS[3:0]
1 1
PREAMBLE[19:12]
0 0
PREAMBLE[27:20]
1 0
RM0453
0 0 0 0 0
JEP106CON
[3:0]
0 0 0 1 0 0
PARTNUM[7:0]
0 0 1 1 0 0
PARTNUM
[11:8]
1 1 0 0 0 0
JEP106ID
[6:4]
1 0 1 0 1 1
0 0 0 0 0 0
PREAMBLE[7:0]
0 0 1 1 0 1
PREAMBLE
[11:8]
1 0 0 0 0 0
0 0 0 1 0 1
1 1 0 0 0 1