Table of Contents
Advertisement
Debug support (DBG)
38.13.8
CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_CIDR1)
Address offset: 0xFF4
Reset value: 0x0000 0010
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: component ID bits [15:12] - component class
0x1: ROM table component
Bits 3:0 PREAMBLE[11:8]: component ID bits [11:8]
0x0: Common ID value
38.13.9
CPU2 ROM1 CoreSight component identity register 2
(C2ROM1_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
1426/1454
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
CLASS[3:0]
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PREAMBLE[11:8]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PREAMBLE[19:12]
r
r
r
r
RM0453
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?