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Debug support (DBG)
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
38.13.21 CPU2 ROM2 CoreSight component identity register 3
(C2ROM2_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.13.22 CPU2 ROM2 register map and reset values
Table 286. CPU2 ROM table register map and reset values
Offset Register name
C2ROM2_
MEMTYPER
0xFCC
Reset value
C2ROM2_PIDR4
0xFD0
Reset value
C2ROM2_PIDR0
0xFE0
Reset value
C2ROM2_PIDR1
0xFE4
Reset value
1432/1454
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 2
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[19:12]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[27:20]
r
r
r
r
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
F4KCOUNT
JEP106CON
[3:0]
[3:0]
0
0
0
0
0
1
0
PARTNUM[7:0]
1
1
0
0
0
0
0
JEP106ID
PARTNUM
[3:0]
[11:8]
1
0
1
1
0
1
0
1
0
0
0
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