ST STM32WL55JC Reference Manual page 1434

Debug support (DBG)
Bits 31:15 Reserved, must be kept at reset value.
Bits 11:8 NUM_LIT[3:0]: number of literal address comparators supported (read only)
0x0: No literal comparators supported.
Bits NUM_CODE[6:0]: number of instruction address comparators supported - least significant bits
14,13,12,7,6,5,4 (read only)
0x8: 8 instruction comparators supported
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 KEY: write protect key
A write to BPU_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: BPU enable
0: Disabled
1: Enabled
38.14.2 BPU remap register (BPU_REMAPR)
Address offset: 0x004
Reset value: 0x0000 0000
31 30 29
Res. Res.
RMPSPT
r
15 14 13
Res. Res. Res.
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 RMPSPT: Flash memory patch remap
Indicates whether Flash memory patch remap is supported (read only).
0: Remapping not supported.
Bits 28:0 Reserved, must be kept at reset value.
38.14.3 BPU comparator register x (BPU_COMPxR)
Address offset: 0x008 + 0x004 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31 30 29 28
REPLACE[1:0] Res.
rw rw rw
15 14 13 12
rw rw rw rw
1434/1454
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
27 26 25
rw rw rw
11 10 9
COMP[13:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22 21
COMP[26:14]
rw rw rw rw
8 7 6
rw rw rw rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
20 19 18
rw rw rw
5 4 3 2
rw rw rw
RM0453
17 16
Res. Res.
1 0
Res. Res.
17 16
rw rw
1 0
ENABL
Res.
E
rw