Pwm Mode; Figure 253. Output Compare Mode, Toggle On Oc1 - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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General-purpose timers (TIM16/TIM17)
TIM1_CNT
0039
TIM1_CCR1
OC1REF= OC1
27.3.9

PWM mode

Pulse Width Modulation mode allows a signal to be generated with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The TIM16/TIM17 are capable of upcounting only. Refer to
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
'1'. If the compare value is 0 then OCxRef is held at '0'.
aligned PWM waveforms in an example where TIMx_ARR=8.
918/1461

Figure 253. Output compare mode, toggle on OC1

Write B201h in the CC1R register
003A
003B
003A
Interrupt generated if enabled
RM0453 Rev 1
Match detected on CCR1
Figure 254
B200
B201
B201
MS31092V1
Upcounting mode on page
shows some edge-
RM0453
906.

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