Tim1 Status Register (Tim1_Sr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Advanced-control timer (TIM1)

Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE: Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

TIM1 status register (TIM1_SR)

Address offset: 0x10

Reset value: 0x0000 0000

CC4OF CC3OF CC2OF CC1OF

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 CC6IF: Compare 6 interrupt flag

Bit 16 CC5IF: Compare 5 interrupt flag

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 SBIF: System Break interrupt flag

Bit 12 CC4OF: Capture/Compare 4 overcapture flag

Bit 11 CC3OF: Capture/Compare 3 overcapture flag

Bit 10 CC2OF: Capture/Compare 2 overcapture flag

Refer to CC1IF description (Note: Channel 6 can only be configured as output)

Refer to CC1IF description (Note: Channel 5 can only be configured as output)

This flag is set by hardware as soon as the system break input goes active. It can be

cleared by software if the system break input is not active.

This flag must be reset to re-start PWM operation.

0: No break event occurred.

1: An active level has been detected on the system break input. An interrupt is generated if

BIE=1 in the TIMx_DIER register.

Refer to CC1OF description

RM0453 Rev 1

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