Lpuart Registers; Lpuart Control Register 1 [Alternate] (Lpuart_Cr1) - ST STM32WL5 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
1. The LPUART can wake up the device from Stop mode only if the peripheral instance supports the Wakeup from Stop mode
feature. Refer to Section 36.3: LPUART implementation
2. RXFF flag is asserted if the LPUART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in
LPUART_RDR. In Stop mode, LPUART_RDR is not clocked. As a result, this register is not written and once n data are
received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).
3. When OVRDIS = 0.
36.7

LPUART registers

Refer to
The peripheral registers have to be accessed by words (32 bits).
36.7.1

LPUART control register 1 [alternate] (LPUART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29
RXF FIFO
TXFEIE
FIE EN
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15 14 13
Res. CMIE MME
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Bit 31 RXFFIE:RXFIFO Full interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when RXFF = 1 in the LPUART_ISR register
Bit 30 TXFEIE:TXFIFO empty interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when TXFE = 1 in the LPUART_ISR register
Bit 29 FIFOEN:FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
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Section 1.2 on page 58
28 27 26 25
M1 Res. Res.
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12 11 10 9
M0 WAKE PCE PS
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for the list of supported Stop modes.
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
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8 7 6
TXFN RXFN
PEIE TCIE
FIE
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RM0453 Rev 1
21 20 19 18
DEDT[4:0]
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5 4 3 2
IDLEIE TE RE
EIE
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RM0453
17 16
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1 0
UESM UE
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