Figure 294. Transfer Bus Diagrams For I2C Master Transmitter - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Inter-integrated circuit (I2C) interface
Example I2C master transmitter 2 bytes, automatic end mode (STOP)
NBYTES
INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
Example I2C master transmitter 2 bytes, software end mode (RESTART)
NBYTES
INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START
1086/1461

Figure 294. Transfer bus diagrams for I2C master transmitter

TXIS
TXIS
S
Address
A
data1
INIT
EV1 EV2
TXE
xx
TXIS TXIS
S Address
A
INIT
EV1 EV2
TXE
xx
A
data2
A
P
2
TC
data1
A
data2
A
2
RM0453 Rev 1
legend:
ReS
Address
EV3
RM0453
transmission
reception
SCL stretch
legend:
transmission
reception
SCL stretch
MS19862V2

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