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Debug support (DBG)
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 APPCLEAR[3:0]: channel event clearing
0000: No effect
XXX1: Clears event on Channel 0.
XX1X: Clears event on Channel 1.
X1XX: Clears event on Channel 2.
1XXX: Clears event on Channel 3.
CTI application pulse register (CTI_APPPULSER)
Address offset: 0x01C
Reset value: 0x0000 0000
w
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 APPPULSE[3:0]: pulse channel event
This register clears itself immediately.
0000: No effect
XXX1: Generates pulse on Channel 0.
XX1X: Generates pulse on Channel 1.
X1XX: Generates pulse on Channel 2.
1XXX: Generates pulse on Channel 3.
CTI trigger in x enable register (CTI_INENRx)
Address offset: 0x020 + 0x004 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
1370/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
APPPULSE[3:0]
w
w
w
w
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
TRIGINEN[3:0]
rw
rw
rw
rw
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