Syscfg Cpu1 Interrupt Mask Register 2 (Syscfg_Imr2); Syscfg Cpu2 Interrupt Mask Register 1 (Syscfg_C2Imr1) - ST STM32WL5 Series Reference Manual

System configuration controller (SYSCFG)
11.2.12

SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2)

Address offset: 0x104
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU1
0: PVD interrupt forwarded to CPU1
1. PVD interrupt to CPU1 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU1
0: PVM3 interrupt forwarded to CPU1
1. PVM3 interrupt to CPU1 masked
Bits 17:0 Reserved, must be kept at reset value.
11.2.13

SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1)

Address offset: 0x108
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
Res. Res. DACIM ADCIM
rw
440/1461
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
rw rw rw rw
12 11 10 9
Res.
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22 21
rw rw rw rw
8 7 6
PKAIM Res. RCCIM
rw rw rw
RM0453 Rev 1
21 20 19 18
Res. PVDIM Res.
rw rw
5 4 3 2
Res. Res. Res. Res.
20 19 18
rw rw rw
5 4 3 2
Res.
rw rw
RM0453
17 16
Res. Res.
1 0
Res. Res.
17 16
EXTI0IM
rw rw
1 0
rw rw