Lpuart Functional Description; Lpuart Block Diagram; Figure 332. Lpuart Block Diagram - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

LPUART functional description

lpuart_tx_dma

lpuart_rx_dma

lpuart_ker_ck

The simplified block diagram given in

The lpuart_pclk clock domain

The lpuart_pclk clock signal feeds the peripheral bus interface. It must be active when

accesses to the LPUART registers are required.

The lpuart_ker_ck kernel clock domain

The lpuart_ker_ck is the LPUART clock source. It is independent of the lpuart_pclk

and delivered by the RCC. So, the LPUART registers can be written/read even when

the lpuart_ker_ck is stopped.

When the dual clock domain feature is disabled, the lpuart_ker_ck is the same as the

lpuart_pclk clock.

There is no constraint between lpuart_pclk and lpuart_ker_ck: lpuart_ker_ck can be

faster or slower than lpuart_pclk, with no more limitation than the ability for the software to

manage the communication fast enough.

Low-power universal asynchronous receiver transmitter (LPUART)

IRQ Interface

clock domain

DMA Interface

COM Controller

RM0453 Rev 1

lpuart_ker_ck clock domain

flow control

TX Shift Reg

RX Shift Reg

orversampling

lpuart_ker_ck_pres

shows two fully independent clock

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