Figure 285. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0 - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

Hide thumbs Also See for STM32WL5 Series:

Table of Contents

Slave receiver

RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is

set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.

When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an

interrupt is generated.

Figure 285. Transfer sequence flowchart for slave receiver with NOSTRETCH=0

Inter-integrated circuit (I2C) interface

Slave reception

Slave initialization

I2C_ISR.ADDR

Read ADDCODE and DIR in I2C_ISR

Set I2C_ICR.ADDRCF

I2C_ISR.RXNE

Write I2C_RXDR.RXDATA

RM0453 Rev 1

Do you have a question about the STM32WL5 Series and is the answer not in the manual?