Serial-Wire Debug Port; Table 264. Packet Request - ST STM32WL5 Series Reference Manual

RM0453
IR Data
instruction register
1110 IDCODE
1111 BYPASS
Data registers are described in more detail in the Arm
Specification [1].
38.3.9

Serial-wire debug port

The Serial-wire debug (SWD) protocol uses the two following pins:
•
SWCLK: clock from host to target
•
SWDIO: bi-directional serial data (100 kΩ pull-up required)
Serial data is transferred LSB first, synchronously with the clock.
Each transfer comprises the three phases listed below:
1. a packet request (8 bits) transmitted by the host (see
2. an acknowledge response (3 bits) transmitted by the target (see
3. data transfer (33 bits) transmitted by the host (in case of a write) or by the target (in
case of a read) (see
The data transfer only occurs if the acknowledge response is OK.
Between each phase, if the direction of the data is reversed, a single clock cycle
turn-around time is inserted.
Bit field
0
1
2
4:3
5
6
7
Table 263. JTAG-DP data registers (continued)
Scan chain
length
ID code
32
0x6BA0 0477: Arm
Bypass
1
A single JTCK cycle delay is inserted between JTDI and JTDO.
Table 266)

Table 264. Packet request

Name
Start Must be 1.
– 0: DP register access - see
APnDP
– 1: AP register access - see
– 0: Write request
RnW
– 1: Read request
A(3:2) Address field of the DP or AP registers
Parity Single bit parity of preceding bits
Stop 0
Park Not driven by host, must be read as 1 by the target.
RM0453 Rev 1
Description
®
JTAG debug port ID code
®
Debug Interface Architecture
Table 264)
Description
Table 263 for a list of DP registers
Section 38.5: Access ports
Debug support (DBG)
Table 265)
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