ST STM32WL5 Series Reference Manual page 1257

RM0453
Bit 7 TXFNF: TXFIFO not full
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
Bit 5 RXFNE: RXFIFO not empty
Bit 4 IDLE: Idle line detected
Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line
Low-power universal asynchronous receiver transmitter (LPUART)
TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the
LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag
remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating
that data can not be written into the LPUART_TDR.
The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the
flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in
TXFIFO (TXFNF and TXFE are set at the same time).
An interrupt is generated if the TXFNFIE bit = 1 in the LPUART_CR1 register.
0: Data register is full/Transmit FIFO is full.
1: Data register/Transmit FIFO is not full.
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXFF is set. An interrupt is generated if TCIE = 1 in the LPUART_CR1 register. It is cleared
by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the
LPUART_TDR register.
An interrupt is generated if TCIE = 1 in the LPUART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from
the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the
RXFIFO. It is cleared when the RXFIFO is empty.
The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR
register.
An interrupt is generated if RXFNEIE = 1 in the LPUART_CR1 register.
0: Data is not received
1: Received data is ready to be read.
This bit is set by hardware when an Idle line is detected. An interrupt is generated if
IDLEIE = 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF
in the LPUART_ICR register.
0: No Idle line is detected
1: Idle line is detected
occurs).
If Mute mode is enabled (MME = 1), IDLE is set if the LPUART is not mute (RWU = 0),
whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
RM0453 Rev 1 1257/1461
1266