Tim1 Capture/Compare Mode Register 1 [Alternate]; (Tim1_Ccmr1) - ST STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N consecutive events are needed to
validate a transition on the output:
0000: No filter, sampling is done at f
0001: f
SAMPLING
0010: f
SAMPLING
0011: f
SAMPLING
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
0111: f
SAMPLING
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
1011: f
SAMPLING
1100: f
SAMPLING
1101: f
SAMPLING
1110: f
SAMPLING
1111: f
SAMPLING
Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as
soon as CC1E='0' (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
25.4.8

TIM1 capture/compare mode register 1 [alternate]

(TIM1_CCMR1)

Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
802/1461
DTS
=f , N=2
CK_INT
=f , N=4
CK_INT
=f , N=8
CK_INT
=f /2, N=6
DTS
=f /2, N=8
DTS
=f /4, N=6
DTS
=f /4, N=8
DTS
=f /8, N=6
DTS
=f /8, N=8
DTS
=f /16, N=5
DTS
=f /16, N=6
DTS
=f /16, N=8
DTS
=f /32, N=5
DTS
=f /32, N=6
DTS
=f /32, N=8
DTS
RM0453 Rev 1
RM0453