Lpuart Receive Data Register (Lpuart_Rdr); Lpuart Transmit Data Register (Lpuart_Tdr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Bit 6 TCCF: Transmission complete clear flag

Bit 5 Reserved, must be kept at reset value.

Bit 4 IDLECF: Idle line detected clear flag

Bit 3 ORECF: Overrun error clear flag

Bit 2 NECF: Noise detected clear flag

Bit 1 FECF: Framing error clear flag

Bit 0 PECF: Parity error clear flag

LPUART receive data register (LPUART_RDR)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value

Address offset: 0x28

Reset value: 0x0000 0000

Low-power universal asynchronous receiver transmitter (LPUART)

Writing 1 to this bit clears the TC flag in the LPUART_ISR register.

Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register.

Writing 1 to this bit clears the ORE flag in the LPUART_ISR register.

Writing 1 to this bit clears the NE flag in the LPUART_ISR register.

Writing 1 to this bit clears the FE flag in the LPUART_ISR register.

Writing 1 to this bit clears the PE flag in the LPUART_ISR register.

Contains the received data character.

The RDR register provides the parallel interface between the input shift register and the

internal bus (see

When receiving with the parity enabled, the value read in the MSB bit is the received parity

RM0453 Rev 1

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