Lpuart Fifos And Thresholds; Figure 333. Lpuart Word Length Programming - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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LPUART FIFOs and thresholds

The LPUART can operate in FIFO mode.

The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The

FIFO mode is enabled by setting FIFOEN bit (bit 29) in LPUART_CR1 register.

Since 9 bits the maximum data word length is 9 bits, the TXFIFO is 9-bits wide. However the

RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store

Low-power universal asynchronous receiver transmitter (LPUART)

9-bit word length (M = 01 ), 1 Stop bit

8-bit word length (M = 00 ), 1 Stop bit

7-bit word length (M = 10 ), 1 Stop bit

** LBCL bit controls last data clock pulse

RM0453 Rev 1

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