Cpu1 Rom Coresight Component Identity Register 3 (Rom_Cidr3); Cpu1 Rom Table Register Map And Reset Values; Table 278. Cpu1 Rom Table Register Map And Reset Values - ST STM32WL5 Series Reference Manual

RM0453
38.8.10

CPU1 ROM CoreSight component identity register 3 (ROM_CIDR3)

Address offset: 0xFFC
Reset value: 0x0000 00B1
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.8.11

CPU1 ROM table register map and reset values

Table 278. CPU1 ROM table register map and reset values

Offset Register name
ROM_MEMTYPER
0xFCC
Reset value
ROM_PIDR4
0xFD0
Reset value
0xFD4-
Reserved
0xFDC
ROM_PIDR0
0xFE0
Reset value
ROM_PIDR1
0xFE4
Reset value
ROM_PIDR2
0xFE8
Reset value
ROM_PIDR3
0xFEC
Reset value
ROM_CIDR0
0xFF0
Reset value
ROM_CIDR1
0xFF4
Reset value
ROM_CIDR2
0xFF8
Reset value
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0453 Rev 1
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
PREAMBLE[27:20]
r r r r
Reserved.
Debug support (DBG)
19 18 17 16
Res. Res. Res. Res.
3 2 1 0
r r r r
F4KCOUNT JEP106CON
[3:0] [3:0]
0 0 0 0 0 0 0 0
PARTNUM[7:0]
1 0 0 1 0 1 1 1
JEP106ID PARTNUM
[3:0] [11:8]
0 0 0 0 0 1 0 0
REVISION JEP106ID
[3:0] [6:4]
0 0 0 0 1 0 1 0
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0 1
PREAMBLE
CLASS[3:0]
[11:8]
0 0 0 1 0 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0 1
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