Data Transfer; Figure 279. Data Reception - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Inter-integrated circuit (I2C) interface

Data transfer

The data transfer is managed through transmit and receive data registers and a shift

The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is

received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If

RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line

is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th

SCL pulse (before the acknowledge pulse).

Shift register

RM0453 Rev 1

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