Bidirectional Break Inputs; Figure 174. Pwm Output State Following Brk Assertion (Ossi=0) - ST STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)
BRK
OCx
I/O state
25.3.17

Bidirectional break inputs

The TIM1 are featuring bidirectional break I/Os, as represented on
They allow the following:
•
A board-level global break signal available for signaling faults to external MCUs or gate
drivers, with a unique pin being both an input and an output status pin
• Internal break sources and multiple external open drain comparator outputs ORed
together to trigger a unique break event, when multiple internal and external break
sources must be merged
The break and break2 inputs are configured in bidirectional mode using the BKBID and
BK2BID bits in the TIMxBDTR register. The BKBID programming bits can be locked in read-
only mode using the LOCK bits in the TIMxBDTR register (in LOCK level 1 or above).
The bidirectional mode is available for both the break and break2 inputs, and require the I/O
to be configured in open-drain mode with active low polarity (using BKINP, BKP, BK2INP
and BK2P bits). Any break request coming either from system (e.g. CSS), from on-chip
peripherals or from break inputs forces a low level on the break input to signal the fault
event. The bidirectional mode is inhibited if the polarity bits are not correctly set (active high
polarity), for safety purposes.
The break software events (BG and B2G) also cause the break I/O to be forced to '0' to
indicate to the external components that the timer has entered in break state. However, this
is valid only if the break is enabled (BK(2)E = 1). When a software break event is generated
with BK(2)E = 0, the outputs are put in safe state and the break flag is set, but there is no
effect on the break(2) I/O.
A safe disarming mechanism prevents the system to be definitively locked-up (a low level on
the break input triggers a break which enforces a low level on the same input).
When the BKDSRM (BK2DSRM) bit is set to 1, this releases the break output to clear a fault
signal and to give the possibility to re-arm the system.
At no point the break protection circuitry can be disabled:
•
The break input path is always active: a break event is active even if the BKDSRM
(BK2DSRM) bit is set and the open drain control is released. This prevents the PWM
output to be re-started as long as the break condition is present.
•
The BK(2)DSRM bit cannot disarm the break protection as long as the outputs are
enabled (MOE bit is set) (see
772/1461

Figure 174. PWM output state following BRK assertion (OSSI=0)

Deadtime
Active Inactive
RM0453 Rev 1
I/O state defined by the GPIO controller (HI-Z)
I/O state defined by the GPIO controller (HI-Z)
Table 177)
Disabled
MS34107V1
Figure 175.
RM0453