Lpuart Prescaler Register (Lpuart_Presc) - ST STM32WL5 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Note: This register must be written only when TXE/TXFNF = 1.
36.7.12

LPUART prescaler register (LPUART_PRESC)

This register can only be written when the LPUART is disabled (UE
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PRESCALER[3:0]: Clock prescaler
The LPUART input clock can be divided by a prescaler:
Note: When PRESCALER is programmed with a value different of the allowed ones,
1264/1461
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure
When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0000: input clock not divided
0001: input clock divided by 2
0010: input clock divided by 4
0011: input clock divided by 6
0100: input clock divided by 8
0101: input clock divided by 10
0110: input clock divided by 12
0111: input clock divided by 16
1000: input clock divided by 32
1001: input clock divided by 64
1010: input clock divided by 128
1011: input clock divided by 256
Remaining combinations: Reserved.
programmed prescaler value is 1011 i.e. input clock divided by 256.
332).
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 1
0).
=
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. PRESCALER[3:0]
rw rw
RM0453
17 16
Res. Res.
1 0
rw rw