Cpu1 Rom Table - ST STM32WL5 Series Reference Manual

Debug support (DBG)
Offset Register name
CTI_PIDR4
0xFD0
Reset value
0xFD4to
Reserved
0xFDC
CTI_PIDR0
0xFE0
Reset value
CTI_PIDR1
0xFE4
Reset value
CTI_PIDR2
0xFE8
Reset value
CTI_PIDR3
0xFEC
Reset value
CTI_CIDR0
0xFF0
Reset value
CTI_CIDR1
0xFF4
Reset value
CTI_CIDR2
0xFF8
Reset value
CTI_CIDR3
0xFFC
Reset value
Refer to
register boundary addresses.
38.8

CPU1 ROM table

The ROM table is a CoreSight component that contains the base addresses of all the
CoreSight debug components accessible via the AHB-AP. This table allows a debugger to
discover the topology of the CoreSight system automatically.
There is one ROM table in the CPU1 sub-system. This table is pointed to by the AP_BASER
register in the CPU1 AHB-AP. It contains the base address pointer for the system control
space (SCS) registers, which allow the debugger to identify the CPU core, as well as the
FPB, DWT, and CTI.
The CPU1 ROM table (see
space, from 0xE00FF000 to 0xE00FFFFC.
1384/1461
Table 276. CTI register map and reset values (continued)
Section 38.8: CPU1 ROM table
Table
Reserved
and Section 38.13: CPU2 ROM tables
277) occupies a 4-Kbyte, 32-bit wide chunk of address
RM0453 Rev 1
RM0453
F4KCOUNT JEP106CON
[3:0] [3:0]
0 0 0 0 0 1 0 0
PARTNUM[7:0]
0 0 0 0 0 1 1 0
JEP106ID PARTNUM
[3:0] [11:8]
1 0 1 1 1 0 0 1
REVISION JEP106ID
[3:0] [6:4]
0 1 0 0 1 0 1 1
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0 1
PREAMBLE
CLASS[3:0]
[11:8]
1 0 0 1 0 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0 1
PREAMBLE[27:20]
1 0 1 1 0 0 0 1
for the