Figure 358. Master Full-Duplex Communication With Crc - ST STM32WL5 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
NSS
SCK
BSY
MOSI
SPE
TXE
FTLVL
00
MISO
RXNE
DMA or software control at Rx events
FRLVL
DMA Tx TICF
Assumptions for master full-duplex communication with CRC example:
•
Data size = 16 bit
• CRC enabled
If DMA is used:
•
Number of Tx frames transacted by DMA is set to 2
•
Number of Rx frames transacted by DMA is set to 3
See also
and notes.
1286/1461

Figure 358. Master full-duplex communication with CRC

MSB DTx1
3
Enable Tx/Rx DMA or interrupts
DTx2
DTx1
10 11 10
4
DRx1
1
00
5
: Communication diagrams on page 1283
2
MSB DTx2
DMA or software control at Tx events
LSB DRx2 LSB
DRx1
10 00 10
DMA Rx TICF
for details about common assumptions
RM0453 Rev 1
MSB CRC
00
CRC LSB
DRx2 DRx3
00 10
6
RM0453
1
00
MSv32124V2