Aes Initialization Vector Register 1 (Aes_Ivr1); Aes Initialization Vector Register 2 (Aes_Ivr2); Aes Initialization Vector Register 3 (Aes_Ivr3) - ST STM32WL5 Series Reference Manual

AES hardware accelerator (AES)
Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]
Refer to
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The AES_IVRx registers may be written only when the AES peripheral is disabled
23.7.10

AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
23.7.11

AES initialization vector register 2 (AES_IVR2)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
23.7.12

AES initialization vector register 3 (AES_IVR3)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
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15 14 13
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694/1461
Section 23.4.15: AES initialization vector registers on page 683
28 27 26 25
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12 11 10 9
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28 27 26 25
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28 27 26 25
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12 11 10 9
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24 23 22
IVI[63:48]
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8 7 6
IVI[47:32]
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24 23 22
IVI[95:80]
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8 7 6
IVI[79:64]
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24 23 22
IVI[127:112]
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8 7 6
IVI[111:96]
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RM0453 Rev 1
for description of the
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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RM0453
17 16
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1 0
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17 16
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1 0
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17 16
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1 0
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