Dma Channel X Number Of Data To Transfer Register (Dma_Cndtrx) - ST STM32WL5 Series Reference Manual

RM0453
Bit 2 HTIE: half transfer interrupt enable
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
13.6.4

DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 NDT[17:0]: number of data to transfer (0 to 2
This field is updated by hardware when the channel is enabled:
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This field is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
privileged/secure mode)
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
– It is decremented after each single DMA 'read followed by write' transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Direct memory access controller (DMA)
24 23 22
Res. Res. Res. Res.
8 7 6
NDT[15:0]
rw rw rw
18
- 1)
RM0453 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
NDT[17:16]
rw rw
1 0
rw rw
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