Nss Pulse Mode; Ti Mode; Figure 360. Nssp Pulse Generation In Motorola Spi Master Mode - ST STM32WL5 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt
is generated on the NSS error detection. In this case, the SPI should be disabled because
data consistency is no longer guaranteed and communications should be reinitiated by the
master when the slave SPI is enabled again.
37.5.12

NSS pulse mode

This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if
the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first
edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is
generated between two consecutive data frame transfers when NSS stays at high level for
the duration of one clock period at least. This mode allows the slave to latch data. NSSP
pulse mode is designed for applications with a single master-slave pair.
Figure 360

Figure 360. NSSP pulse generation in Motorola SPI master mode

sampling
NSS
output
SCK
output
MOSI
output
MISO
input Do not care
t
SCK
Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.
37.5.13

TI mode

TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ when the current transaction finishes (see
rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for
the MISO signal to become HiZ (t
1290/1461
illustrates NSS pin management when NSSP pulse mode is enabled.
Master continuous transfer (CPOL = 1; CPHA = 0; NSSP= 1)
sampling sampling
MSB
MSB LSB
4-bits to 16-bits
sampling
LSB
Do not care
t
t t
SCK
SCK SCK
) depends on internal resynchronization and on the
release
RM0453 Rev 1
sampling sampling
MSB LSB
MSB
LSB
4-bits to 16-bits
Figure 361). Any baud
RM0453
Do not care
t
SCK
MS19838V1