Figure 171. Break And Break2 Circuitry Overview - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Advanced-control timer (TIM1)

All sources are ORed before entering the timer BRK or BRK2 inputs, as per

RAM parity Error

Double ECC Error

COMP1 output

COMP2 output

BKIN2 inputs

COMP1 output

COMP2 output

An asynchronous (clockless) operation is only guaranteed when the programmable filter is

disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or

the CSS) must be used to guarantee that break events are handled.

Figure 171. Break and Break2 circuitry overview

System break requests

Application break requests

Application break requests

RM0453 Rev 1

Software break requests: BG

Software break requests: B2G

BRK2 request

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