Dp Read Buffer Register (Dp_Buffr); Dp Target Identification Register (Dp_Targetselr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
Bits 27:8 Reserved, must be kept at reset value.
Bits 7:4 APBANKSEL[3:0]: AP register bank selection
Selects the 4-word register bank on the active AP for the next transaction.
Bits 3:0 DPBANKSEL[3:0]: DP register bank selection
Selects the register at address 0x4 of the debug port.
0x0: DP_CTRLSTATR
0x1: DP_DLCR
0x2: DP_TARGETIDR
0x3: DP_DLPIDR
0x4 to 0xF: reserved
38.4.9

DP read buffer register (DP_BUFFR)

Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
Bits 31:0 RDBUFF[31:0]: Contains the value returned by the last AP read access.
The value returned by an AP read access can either be obtained using a second read access
to the same address, which initiates a new transaction on the corresponding bus, or else it
can be read from this register, in which case no new AP transaction occurs.
38.4.10

DP target identification register (DP_TARGETSELR)

Address offset: 0x0C
Reset value: 0xXXXX XXXX
31
30
29
28
TINSTANCE[3:0]
w
w
w
w
15
14
13
12
TPARTNO[3:0]
w
w
w
w
1340/1461
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
27
26
25
w
w
w
11
10
9
w
w
w
24
23
22
RDBUFF[31:16]
r
r
r
8
7
6
RDBUFF[15:0]
r
r
r
24
23
22
21
TPARTNO[15:4]
w
w
w
8
7
6
TDESIGNER[10:0]
w
w
w
RM0453 Rev 1
21
20
19
18
r
r
r
r
5
4
3
2
r
r
r
r
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
RM0453
17
16
r
r
1
0
r
r
17
16
w
w
1
0
Res.
w

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