Table 273. Cpu2 Cti Outputs; Table 274. Cpu1 Cti Inputs; Table 275. Cpu1 Cti Outputs - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Output signal Destination component

Source signal

Source signal

There are four event channels in the CTM, thus enabling up to four, parallel, bidirectional

connections between trigger inputs and outputs on different CTIs. To connect input number

m on CTIx to output number n on CTIy, the input must be connected to an event channel p

using the CTI_INENRm register of CTIx. The same channel p must be connected to the

output using the CTI_OUTENRn register of CTIy.

Table 273. CPU2 CTI outputs

Source component

Source component

CPU2 halt request - Puts CPU2 in debug mode.

CPU2 restart request - CPU2 exits debug mode.

CPU1 halted - indicates CPU1 is in debug mode.

CPU1 halt request - Puts CPU1 in debug mode.

CPU1 restart request - CPU1 exits debug mode

RM0453 Rev 1

Debug support (DBG)

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