Dp Target Identification Register (Dp_Targetidr); Dp Data Link Protocol Identification Register (Dp_Dlpidr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:8 TURNROUND[1:0]: tristate period for SWDIO
0x0: 1 data bit period
0x1: 2 data bit periods
0x2: 3 data bit periods
0x3: 4 data bit periods
Bits 7:0 Reserved, must be kept at reset value.
38.4.5

DP target identification register (DP_TARGETIDR)

Address offset: 0x04
and DP_SELECTR.DPBANKSEL = 2
Reset value: 0x0497 0041
31
30
29
28
TREVISION[3:0]
r
r
r
r
15
14
13
12
TPARTNO[3:0]
r
r
r
r
Bits 31:28 TREVISION[3:0]: target revision
0x0: revision 1
Bits 27:12 TPARTNO[15:0]: target part number
0x4970: STM32WL5x
Bits 11:1 TDESIGNER[10:0]: target designer JEDEC code.
0x020: STMicroelectronics
Bit 0 Reserved, must be kept at reset value.
38.4.6

DP data link protocol identification register (DP_DLPIDR)

Address offset: 0x04
and DP_SELECTR.DPBANKSEL = 3
Reset value: 0x0000 0001
31
30
29
28
TINSTANCE[3:0]
r
r
r
r
15
14
13
12
Res.
Res.
Res.
Res.
1338/1461
27
26
25
24
r
r
r
r
11
10
9
8
r
r
r
r
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
TPARTNO[15:4]
r
r
r
r
7
6
5
4
TDESIGNER[10:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0453
19
18
17
16
r
r
r
3
2
1
0
Res.
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PROTSVN[3:0]
r
r
r
r
r

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