Timx Repetition Counter Register (Timx_Rcr)(X = 16 To 17); Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 16 To 17) - ST STM32WL5 Series Reference Manual

General-purpose timers (TIM16/TIM17)
27.4.12

TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)

Address offset: 0x30
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition counter value
27.4.13

TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)

Address offset: 0x34
Reset value: 0x0000
15 14 13
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Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
942/1461
12 11 10 9
Res. Res. Res.
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode.
12 11 10 9
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If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
8 7 6
Res.
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8 7 6
CCR1[15:0]
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RM0453 Rev 1
5 4 3 2
REP[7:0]
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5 4 3 2
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RM0453
1 0
rw rw
1 0
rw rw