Dp Register Map And Reset Values; Table 268. Dp Register Map And Reset Values - ST STM32WL5 Series Reference Manual

RM0453
Bits 31:28 TINSTANCE[3:0]: target instance number
Defines the instance number for the target device in a multi-drop system. These bits must be
written with the same value used for DP_DLPIDR.TINSTANCE to select this device.
Bits 27:12 TPARTNO[15:0]: target part number
Defines the part number for the target device. These bits must be written with the same value
used for DP_TARGETIDR.TPARTNO to select this device.
Bits 11:1 TDESIGNER[10:0]: target designer JEDEC code
Defines the JEDEC code for the target device. These bits must be written with the same
value used for DP_TARGETIDR.TDESIGNER to select this device.
Bit 0 Reserved, must be kept at reset value.
38.4.11

DP register map and reset values

These registers are not on the CPU memory bus and are only accessed through SW-DP
and JTAG-DP debug interface.
The debug port address is 2-bit wide, defined in the JTAG-DP register DPACC or SW-DP
packet request A[3:2] field.
Offset Register name
DP_DPIDR
0x00
Reset value
DP_ABORTR
0x00
Reset value
DP_CTRLSTATR
(1)
0x04
Reset value
DP_DLCR
(2)
0x04
Reset value
DP_TARGETIDR
(3)
0x04
Reset value

Table 268. DP register map and reset values

PARTNO[7:0]
0 1 0 1 1 0 1 1 1
0 0 0
0 0 0 0 0 1 0 0 1
0 1 0 0 0 0
TRNCNT[11:0]
0 0 0 0 0 0 0 0 0
TPARTNO[15:0]
0 0 1 0 1 1 1 0 0
RM0453 Rev 1
Debug support (DBG)
DESIGNER[10:0]
1 0 0 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0
0 0
TDESIGNER[10:0]
0 0 0 0 0 0 0 1 0
1 0 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0
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