ST STM32WL5 Series Reference Manual page 1376

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
CTI authentication status register (CTI_AUTHSTATR)
Address offset: 0xFB8
Reset value: 0x0000 000A
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 SNID[1:0]: security level for secure non-invasive debug
0x0: Not implemented
Bits 5:4 SID[1:0]: security level for secure invasive debug
0x0: Not implemented
Bits 3:2 NSNID[1:0]: security level for non-secure non-invasive debug
0x2: Disabled
0x3: Enabled
Bits 1:0 NSID[1:0]: security level for non-secure invasive debug
0x2: Disabled
0x3: Enabled
CTI device configuration register (CTI_DEVIDR)
Address offset: 0xFC8
Reset value: 0x0004 0800
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
NUMTRIG[7:0]
r
r
r
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:16 NUMCH[3:0]: number of ECT channels
0x4: 4 channels
Bits 15:8 NUMTRIG[7:0]: number of ECT triggers
0x8: 8 trigger inputs and 8 trigger outputs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 EXTMUXNUM[4:0]: number of trigger input/output multiplexers
0x0: None
1376/1461
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
r
r
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
SNID[1:0]
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
r
RM0453 Rev 1
21
20
19
18
Res.
Res.
Res.
5
4
3
2
SID[1:0]
NSNID[1:0]
r
r
r
r
21
20
19
18
Res.
NUMCH[3:0]
r
r
5
4
3
2
EXTMUXNUM[4:0]
r
r
r
RM0453
17
16
Res.
Res.
1
0
NSID[1:0]
r
r
17
16
r
r
1
0
r
r

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