Figure 133. Counter Timing Diagram, Internal Clock Divided By 4; Figure 134. Counter Timing Diagram, Internal Clock Divided By N - ST STM32WL5 Series Reference Manual

Advanced-control timer (TIM1) RM0453

Figure 133. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31080V2

Figure 134. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
1F 00
Counter register 20
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31081V2
736/1461 RM0453 Rev 1