Single Conversion Mode (Cont = 0); Continuous Conversion Mode (Cont = 1) - ST STM32WL5 Series Reference Manual

Analog-to-digital converter (ADC)
18.3.10 Single conversion mode (CONT
In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note: To convert a single channel, program a sequence with a length of 1.
18.3.11 Continuous conversion mode (CONT
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
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