Table 103. Latency Between Trigger And Start Of Conversion - ST STM32WL5 Series Reference Manual

Analog-to-digital converter (ADC)
ADC clock source
HSI16, SYSCLK or
PLLPCLK
PCLK divided by 2
PCLK divided by 4
PCLK divided by 1
1. Refer to the device datasheet for the maximum ADC_CLK frequency.
2. Selected with ADCSEL bitfield of the RCC_CCIPR register
Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the
PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle
and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and
clock controller section). If an internal source clock is selected, the AHB and APB prescalers
do not divide the clock.
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Table 103. Latency between trigger and start of conversion

CKMODE[1:0]
(2)
Latency between the trigger event
00 Latency is not deterministic (jitter)
Latency is deterministic (no jitter) and equal to
01
3.25 ADC clock cycles
Latency is deterministic (no jitter) and equal to
10
3.125 ADC clock cycles
Latency is deterministic (no jitter) and equal to
11
3 ADC clock cycles
RM0453 Rev 1
(1)
and the start of conversion
RM0453