Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 251. Capture/Compare Channel 1 Main Circuit - ST STM32WL5 Series Reference Manual

General-purpose timers (TIM16/TIM17)

Figure 250. Capture/compare channel (example: channel 1 input stage)

TI1[0]
TI1[1..15]
f
DTS
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Input mode
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
914/1461
TI1F_Rising
Filter Edge
TI1F_Falling
downcounter detector
ICF[3:0]
TIMx_CCER
TIMx_CCMR1
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)

Figure 251. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
Capture/compare preload register
Capture
compare shadow register
TI1F_ED
0
TI1FP1
1
TI2FP1
CC1P
TRC
(from slave mode
controller)
0
1
16/32-bit
Compare
transfer
Comparator
Counter
RM0453 Rev 1
To the slave mode controller
01
IC1 Divider
10
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
TIMx_CCER
TIMx_CCMR1
Output mode
CC1S[1]
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
RM0453
IC1PS
CC1E
MSv40936V1
OC1PE
TIMx_CCMR1
MSv63030V1