ST STM32WL5 Series Reference Manual page 1141

RM0453
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, it is handled in the same way as a data character reception
except that an interrupt is generated if the IDLEIE bit is set.
Overrun error
•
FIFO mode disabled
An overrun error occurs if a character is received and RXNE has not been reset.
Data can not be transferred from the shift register to the RDR register until the RXNE
bit is cleared. The RXN E flag is set after every byte reception.
An overrun error occurs if RXNE flag is set when the next data is received or the
previous DMA request has not been serviced. When an overrun error occurs:
–
–
–
–
•
FIFO mode enabled
An overrun error occurs when the shift register is ready to be transferred and the
receive FIFO is full.
Data can not be transferred from the shift register to the USART_RDR register until
there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is
not empty.
An overrun error occurs if the RXFIFO is full and the shift register is ready to be
transferred. When an overrun error occurs:
–
–
–
–
The ORE bit is reset by setting the ORECF bit in the USART_ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost.
When the FIFO mode is disabled, there are two possibilities
•
if RXNE = 1, then the last valid data is stored in the receive register (RDR) and can be
read,
•
if RXNE = 0, the last valid data has already been read and there is nothing left to be
read in the RDR register. This case can occur when the last valid data is read in the
RDR register at the same time as the new (and lost) data is received.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
generated and data can be read from RXFIFO when the RXFIFO threshold is
reached. In this case, the CPU can read a block of data defined by the
programmed threshold.
the ORE bit is set;
the RDR content is not lost. The previous data is available by reading the
USART_RDR register.
the shift register is overwritten. After that, any data received during overrun is lost.
an interrupt is generated if either the RXNEIE or the EIE bit is set.
The ORE bit is set.
The first entry in the RXFIFO is not lost. It is available by reading the
USART_RDR register.
The shift register is overwritten. After that point, any data received during overrun
is lost.
An interrupt is generated if either the RXFNEIE or EIE bit is set.
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