Lptim Configuration Register (Lptim_Cfgr) - ST STM32WL5 Series Reference Manual

Low-power timer (LPTIM)
Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable
0: EXTTRIG interrupt disabled
1: EXTTRIG interrupt enabled
Bit 1 ARRMIE: Autoreload match Interrupt Enable
0: ARRM interrupt disabled
1: ARRM interrupt enabled
Bit 0 CMPMIE: Compare match Interrupt Enable
0: CMPM interrupt disabled
1: CMPM interrupt enabled
Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to '0')
28.7.4

LPTIM configuration register (LPTIM_CFGR)

Address offset: 0x00C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TRIGSEL[2:0] Res.
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 Reserved, must be kept at reset value.
Bits 28:25 Reserved, must be kept at reset value.
Bit 24 ENC: Encoder mode enable
The ENC bit controls the Encoder mode
0: Encoder mode disabled
1: Encoder mode enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 28.3: LPTIM
Bit 23 COUNTMODE: counter mode enabled
The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
0: the counter is incremented following each internal clock pulse
1: the counter is incremented following each valid clock pulse on the LPTIM external Input1
Bit 22 PRELOAD: Registers update mode
The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CMP registers update
modality
0: Registers are updated after each APB bus write access
1: Registers are updated at the end of the current LPTIM period
972/1461
28 27 26 25
Res. Res. Res.
12 11 10 9
PRESC[2:0]
rw rw rw
implementation.
24 23 22
COUNT PRE
ENC
MODE LOAD
rw rw rw
8 7 6
Res. TRGFLT[1:0]
rw rw
RM0453 Rev 1
21 20 19 18
WAV
WAVE TIMOUT TRIGEN[1:0]
POL
rw rw rw rw
5 4 3 2
Res. CKFLT[1:0] CKPOL[1:0]
rw rw rw
RM0453
17 16
Res.
rw
1 0
CKSEL
rw rw