Rtc Masked Interrupt Status Register (Rtc_Misr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Real-time clock (RTC)

RTC masked interrupt status register (RTC_MISR)

Address offset: 0x54

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 SSRUMF: SSR underflow masked flag

Bit 5 ITSMF: Internal timestamp masked flag

Bit 4 TSOVMF: Timestamp overflow masked flag

Bit 3 TSMF: Timestamp masked flag

Bit 2 WUTMF: Wakeup timer masked flag

Bit 1 ALRBMF: Alarm B masked flag

This flag is set by hardware when the alarm B interrupt occurs.

Bit 0 ALRAMF: Alarm A masked flag

This flag is set by hardware when the SSR underflow interrupt occurs.

This flag is set by hardware when a timestamp on the internal event occurs and

timestampinterrupt is raised.

This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.

It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,

an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit

This flag is set by hardware when a timestamp interrupt occurs.

If ITSF flag is set, TSF must be cleared together with ITSF.

This flag is set by hardware when the wakeup timer interrupt occurs.

This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1

This flag is set by hardware when the alarm A interrupt occurs.

RM0453 Rev 1

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