Lpuart Control Register 1 [Alternate] (Lpuart_Cr1) - ST STM32WL5 Series Reference Manual

RM0453
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: LPUART enable in Stop mode
When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode.
When this bit is set, the LPUART is able to wake up the MCU from low-power mode,
provided that the LPUART clock selection is HSI or LSE in the RCC.
This bit is set and cleared by software.
0: LPUART not able to wake up the MCU from low-power mode.
1: LPUART able to wake up the MCU from low-power mode. When this function is active,
the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Note: It is recommended to set the UESM bit just before entering low-power mode and clear
Bit 0 UE: LPUART enable
When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the LPUART is kept, but all the status
flags, in the LPUART_ISR are reset. This bit is set and cleared by software.
0: LPUART prescaler and outputs disabled, low-power mode
1: LPUART enabled
Note: To enter low-power mode without generating errors on the line, the TE bit must be reset
36.7.2

LPUART control register 1 [alternate] (LPUART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled
31 30 29
FIFO
Res. Res.
EN
rw
15 14 13
Res. CMIE MME
rw rw
Low-power universal asynchronous receiver transmitter (LPUART)
it on exit from low-power mode.
before and the software must wait for the TC bit in the LPUART_ISR to be set before
resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.
28 27 26 25
M1 Res. Res.
rw rw
12 11 10 9
M0 WAKE PCE PS
rw rw rw rw
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
PEIE TXEIE TCIE RXNEIE IDLEIE
rw rw rw
RM0453 Rev 1
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
TE RE
rw rw rw rw
17 16
rw rw
1 0
UESM UE
rw rw
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